Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl spi

Search list

[VHDL-FPGA-Verilog] C702

Description: 控制HMC702的VHDL程序代码,实际使用是可以的，HMC MODE-HMC702 SPI VHDL code
Platform: | Size: 1024 | Author: 李泽 | Hits:

[VHDL-FPGA-Verilog] Read_SPI_ADC

Description: This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.-This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
Platform: | Size: 1024 | Author: Hossein | Hits:

[VHDL-FPGA-Verilog] SPITX16

Description: 基于状态机的优秀SPI输出程序（以DAC7512为基础，可修改）-VHDL code about SPI
Platform: | Size: 1024 | Author: 颜德飞 | Hits:

[VHDL-FPGA-Verilog] ad_spi

Description: AD2548 SPI读写时序 VHDL-AD2548 SPI
Platform: | Size: 2048 | Author: wei | Hits:

[Other] vspi

Description: SPI串口的内核实现verilog语言和VHDL语言-The serial peripheral interface spi bus
Platform: | Size: 6144 | Author: david | Hits:

[VHDL-FPGA-Verilog] DAC_VHDL

Description: DAC VHDL code using SPI method
Platform: | Size: 7168 | Author: mohamed | Hits:

[VHDL-FPGA-Verilog] spi_verilog_master_slave_latest.tar

Description: 该项目从需要具有强大而简单的以VHDL编写的SPI接口核心开始，用于通用的FPGA到设备接口。 所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing. The resulting cores generate small and efficient circuits, that operate very slow SPI clocks up to over 50MHz SPI clocks.
Platform: | Size: 3072 | Author: asdtgg | Hits:
« 1 2 ... 10 11 12 13 14 15»

CodeBus www.codebus.net